Single Operand Instruction Execution Times

This table indicates the number of clock periods for the single operand
instructions. The number of bus read and write cycles is shown in parenthesis
as (r/w). The number of clock periods and the number of read and write cycles
must be added respectively to those of the effective address calculation
where indicated.


		Single Operand Instruction Execution Times

instruction	size		register	 memory

CLR		byte,word	4(1/0)		 8(1/1) +
		  long		6(1/0)		12(1/2) +
NBCD		  byte		6(1/0)		 8(1/1) +
NEG		byte,word	4(1/0)		 8(1/1) +
		  long		6(1/0)		12(1/2) +
NEGX		byte,word	4(1/0)		 8(1/1) +
		  long		6(1/0)		12(1/2) +
NOT		byte,word	4(1/0)		 8(1/1) +
		  long		6(1/0)		12(1/2) +
Scc		byte,false	4(1/0)		 8(1/1) +
		byte,true	6(1/0)		 8(1/1) +
TAS #		  byte		4(1/0)		10(1/1) +
TST		byte,word	4(1/0)		 4(1/0) +
		  long		4(1/0)		 4(1/0) +

	+ add effective address calculation time
        # This instruction should never be used on the Amiga as its invisiable
          read/write cycle can disrupt system DMA.